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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1 Features
CAS Latency and Frequency
CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166
* Double data rate architecture: two data transfers per clock cycle * Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver * DQS is edge-aligned with data for reads and is center-aligned with data for writes * Differential clock inputs (CK and CK) * Four internal banks for concurrent operation * Data mask (DM) for write data
* DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Burst Lengths: 2, 4, or 8 * CAS Latency: (1.5), 2, 2.5, (3) * Auto Precharge option for each burst access * Auto Refresh and Self Refresh Modes * 7.8ms Maximum Average Periodic Refresh Interval (8K refresh) * 2.5V (SSTL_2 compatible) I/O * VDDQ = 2.5V 0.2V / VDD = 2.5V 0.2V * TSOP66 package * 60 balls BGA w/ 3 depop rows ("chipsize package") 12 mm x 8 mm.
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and
2003-01-09, V1.1
row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Ordering Information
Part Numbera HYB25D256400BT(L)-6 HYB25D256800BT(L)-6 HYB25D256160BT(L)-6 HYB25D256400BT(L)-7 HYB25D256800BT(L)-7 HYB25D256160BT(L)-7 HYB25D256400BT(L)-7F HYB25D256800BT(L)-7F HYB25D256160BT(L)-7F HYB25D256400BT(L)-8 HYB25D256800BT(L)-8 HYB25D256160BT(L)-8 HYB25D256400BC(L)-6 HYB25D256800BC(L)-6 HYB25D256160BC(L)-6 HYB25D256400BC(L)-7 HYB25D256800BC(L)-7 HYB25D256160BC(L)-7 HYB25D256400BC(L)-7F HYB25D256800BC(L)-7F HYB25D256160BC(L)-7F HYB25D256400BC(L)-8 HYB25D256800BC(L)-8 HYB25D256160BC(L)-8 Org. x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 x4 x8 x16 125 100 DDR200 2-2-2 DDR266 143 DDR266A 2.5-3-3 166 2-3-3 133 DDR333 60 Balls P-FBGA 125 100 DDR200 2-2-2 DDR266 143 DDR266A CAS-RCD-RP Latencies 2.5-3-3 Clock (MHz) 166 CAS-RCD-RP Latencies 2-3-3 Clock (MHz) 133 Speed DDR333 Package 66 Pin P-TSOP-II
a. HYB: designator for memory components 25D: DDR-I SDRAMs at Vddq=2.5V 256: 256Mb density 400/800/160: Product variations x4, x8 and x16 B: Die revision B C/T: Package type FBGA and TSOP L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents -5/6/7/7F/8: speed grade - see table
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Pin Configuration (TSOP66)
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 16Mb x 16 32Mb x 8 64Mb x 4
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Pin Configuration (FBGA)
1 VSSQ NC NC NC NC VREF
2 NC VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4
3 VSS DQ3 NC DQ2 DQS DM CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M
7 VDD DQ0 NC DQ1 NC NC WE RAS BA1 A0 A2 VDD
8 NC VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3
9 VDDQ NC NC NC NC NC
1 VSSQ NC NC NC NC VREF
2 DQ7 VDDQ VSSQ VDDQ VSSQ VSS CLK A12 A11 A8 A6 A4
3 VSS DQ6 DQ5 DQ4 DQS DM CLK CKE A9 A7 A5 VSS A B C D E F G H J K L M
7 VDD DQ1 DQ2 DQ3 NC NC WE RAS BA1 A0 A2 VDD
8 DQ0 VSSQ VDDQ VSSQ VDDQ VDD CAS CS BA0 A10/AP A1 A3
9 VDDQ NC NC NC NC NC
(x4)
Top View (see the balls through the package)
1 2 3 VSS A B C D E F G H J K L M 7 VDD DQ2 DQ4 DQ6 8 DQ0 VSSQ VDDQ VSSQ 9 VDDQ DQ1 DQ3 DQ5 DQ7 NC
( x8 )
VSSQ DQ15
DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ DQ8 VREF DQ9
VSSQ UDQS VSS CLK A12 A11 A8 A6 A4 UDM CLK CKE A9 A7 A5 VSS
LDQS VDDQ LDM WE RAS BA1 A0 A2 VDD VDD CAS CS BA0 A10/AP A1 A3
( x 16 )
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Input/Output Functional Description
Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. The standard pinout includes one CS pin. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is being applied. BA0 and BA1 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Address Inputs: Provide the row address for Active commands, and the column address and Auto Precharge bit for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. No Connect: No internal electrical connection is present. Supply Supply Supply Supply Supply DQ Power Supply: 2.5V 0.2V. DQ Ground Power Supply: 2.5V 0.2V. Ground SSTL_2 reference voltage: (VDDQ / 2)
CKE
Input
CS RAS, CAS, WE
Input Input
DM
Input
BA0, BA1
Input
A0 - A12
Input
DQ DQS NC VDDQ VSSQ VDD VSS VREF
Input/Output Input/Output
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Block Diagram (64Mb x 4)
Control Logic
CKE CK CK CS WE CAS RAS
Command Decode
Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder
Bank2
Bank3 CK, CK DLL
Mode Registers
13
8192
Read Latch
Refresh Counter 13
4 4 MUX 4 DQS Generator 1
Sense Amplifiers Bank Control Logic
8192
8
Drivers
13
Bank0 Memory Array (8192 x 1024 x 8)
Data
Address Register
COL0 I/O Gating DM Mask Logic 1024 (x8) Column Decoder 10 8 8 Write FIFO & Drivers
2
2 8
4
4 4
4 clk clk out in Data CK, CK COL0
4
11
Column-Address Counter/Latch 1
COL0
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Receivers
A0-A12, BA0, BA1
2
15
Input Register 1 Mask 1 1 1
DQS 1
DQ0-DQ3, DM DQS
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Block Diagram (32Mb x 8)
Control Logic
CKE CK CK CS WE CAS RAS
Command Decode
Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder
Bank2
Bank3 CK, CK DLL
Mode Registers
13
8192
Read Latch
Refresh Counter 13
8 8 MUX 8 DQS Generator 1
Sense Amplifiers Bank Control Logic
8192
16
Drivers
13
Bank0 Memory Array (8192 x 512x 16)
Data
Address Register
COL0 I/O Gating DM Mask Logic
512 (x16)
2
16
2 16
8
8 8
Column Decoder 9 10 Column-Address Counter/Latch 1 COL0
8 clk clk out in Data CK, CK COL0
8
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Receivers
A0-A12, BA0, BA1
2
16 Write FIFO & Drivers
15
Input Register 1 Mask 1 1 1
DQS 1
DQ0-DQ7, DM DQS
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Block Diagram (16Mb x 16)
CKE CK CK CS WE CAS RAS
Command Decode
Control Logic
Bank1 Row-Address MUX Bank0 Row-Address Latch & Decoder
Bank2
Bank3 CK, CK DLL
Mode Registers
13
8192
Read Latch
Refresh Counter 13
16 16 MUX 16 DQS Generator 1
Sense Amplifiers Bank Control Logic
8192
32
Drivers
13
Bank0 Memory Array (8192 x 256x 32)
Data
Address Register
COL0 I/O Gating DM Mask Logic
256 (x32)
2
32
2 32
16
16 16
Column Decoder 8 9 Column-Address Counter/Latch 1 COL0
16 clk clk out in Data CK, CK COL0
16
2
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional DQ , UDQS and LDQS signals.
Receivers
A0-A11, BA0, BA1
2
32 Write FIFO & Drivers
15
Input Register 1 Mask 1 1 1
DQS 1
DQ0-DQ15, DM LDQS, UDQS
Page 8 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Functional Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following criteria must be met: No power sequencing is specified during power up or power down given the following criteria: VDD and VDDQ are driven from a single power converter output AND VTT meets the specification AND VREF tracks VDDQ/2 or The following relationship must be followed: VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200ms delay prior to applying an executable command. Once the 200ms delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and any executable command. During the 200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a Precharge ALL command should be applied, placing the device in the "all banks idle" state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Register Definition
Mode Register The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements results in unspecified operation. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts.
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Mode Register Operation
BA1 0*
BA0 0*
A12
A11 A10
A9
A8
A7
A6
A5
A4
A3 BT
A2
A1
A0
Address Bus Mode Register
Operating Mode
CAS Latency
Burst Length
A12 - A9 0 0 0
A8 0 1 0
A7 0 0 1
A6 - A0 Valid Valid
Operating Mode Normal operation Do not reset DLL Normal operation in DLL Reset Reserved Reserved A3 0 1 Burst Type Sequential Interleave
-
-
-
CAS Latency
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 (optional) Reserved 1.5 (optional) 2.5 Reserved A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length
A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
* BA0 and BA1 must be 0, 0 to select the Mode Register (vs. the Extended Mode Register).
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Burst Definition
Starting Column Address Burst Length A2 2 0 0 4 1 1 0 0 0 0 8 1 1 1 1 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Order of Accesses Within a Burst
Notes: 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. 3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 12. Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks. CAS latency of 1.5 is an optional feature on this device. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. Required CAS Latencies
CAS Latency = 2, BL = 4
CK CK Command Read NOP CL=2 DQS DQ NOP NOP NOP NOP
CAS Latency = 2.5, BL = 4
CK CK Command Read NOP CL=2.5 DQS DQ NOP NOP NOP NOP
Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self refresh operation. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. I-V curves for the normal and weak drive strength are included in this document.
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Extended Mode Register Definition
BA1 0*
BA0 1*
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2 0
A1 DS
A0 DLL
Address Bus Extended Mode Register
Operating Mode
Drive Strength
An - A3 0 A2 - A0 Valid Operating Mode Normal Operation All other states Reserved 0 1 Normal Weak A1 Drive Strength
-
-
A2 0 must be set to 0 A0 0 * BA0 and BA1 must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register) 1 DLL Enable Disable
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Commands
CommandsDeselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. Active The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and completed before opening a different row in the same bank. Read The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 8, j = don't care] for x16, [i = 9, j = don't care] for x8 and [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Write The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don't care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column location. Precharge The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any
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Read or Write commands being issued to that bank. A precharge command is treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge (tRP) is completed. This is determined as if an explicit Precharge command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Auto Refresh Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an Auto Refresh command. The 256Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8 ms (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Auto Refresh commands can be posted in the system, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 * 7.8 ms (70.2ms). This maximum absolute interval is short enough to allow for DLL updates internal to the DDR SDRAM to be restricted to Auto Refresh cycles, without allowing too much drift in tAC between updates. Self Refresh The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can be issued). Input signals except CKE (low) are "Don't Care" during Self Refresh operation. The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.
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Truth Table 1a: Commands
Name (Function) Deselect (Nop) No Operation (Nop) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set CS H L L L L L L L L RAS X H L H H H L L L CAS X H H L L H H L L WE X H H H L L L H L Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code MNE NOP NOP ACT Read Write BST PRE AR / SR MRS Notes 1, 9 1, 9 1, 3 1, 4 1, 4 1, 8 1, 5 1, 6, 7 1, 2
1. CKE is HIGH for all commands shown except Self Refresh. 2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register.) 3. BA0-BA1 provide bank address and A0-A12 provide row address. 4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. 5. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW. 7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts 9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function) Write Enable Write Inhibit 1. Used to mask write data; provided coincident with the corresponding data. DM L H DQs Valid X Notes 1 1
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Operations
Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A subsequent Active command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive Active commands to the same bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive Active commands to different banks is defined by tRRD.
Activating a Specific Row in a Specific Bank
CK CK CKE CS RAS CAS WE A0-A12 BA0, BA1 RA BA RA = row address. BA = bank address. Don't Care HIGH
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tRCD and tRRD Definition
CK CK Command A0-A12 BA0, BA1
ACT ROW BA x NOP ACT ROW BA y NOP NOP RD/WR COL BA y NOP NOP
tRRD
tRCD
Don't Care
Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on Read Command on page 21. The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is disabled. During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). Read Burst: CAS Latencies (Burst Length = 4) on page 22 shows general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8) on page 23. A Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read data is illustrated on Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4) on page 24. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 25.
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Read Command
CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
CA EN AP
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Read Burst: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK CK Command Address
Read
BA a,COL n
NOP
NOP
NOP
NOP
NOP
CL=2 DQS DQ
DOa-n
CAS Latency = 2.5
CK CK Command Address
Read BA a,COL n NOP NOP NOP NOP NOP
CL=2.5 DQS DQ
DOa-n
DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK CK Command Address
Read NOP Read NOP NOP NOP
BAa, COL n
BAa, COL b
CL=2 DQS DQ
DOa-n DOa-b
CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
Read
BAa,COL b
NOP
NOP
NOP
CL=2.5 DQS DQ
DOa- n DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length = 4, the bursts are concatenated. When burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following DO a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
NOP
NOP
Read
BAa, COL b
NOP
NOP
CL=2 DQS DQ
DO a-n DOa- b
CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
NOP
Read
BAa, COL b
NOP
NOP
NOP
CL=2.5 DQS DQ
DO a-n DOa- b
DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b). Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
Read
BAa, COL x
Read
BAa, COL b
Read
BAa, COL g
NOP
NOP
CL=2 DQS DQ
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b' DOa-g
CAS Latency = 2.5
CK CK Command Address
Read Read Read Read NOP NOP
BAa, COL n
BAa, COL x
BAa, COL b
BAa, COL g
CL=2.5 DQS DQ
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b'
DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted). Reads are to active rows in any banks. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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Data from any Read burst may be truncated with a Burst Terminate command, as shown on Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 27. The Burst Terminate latency is equal to the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command, where x equals the number of desired data element pairs. Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If truncation is necessary, the Burst Terminate command must be used, as shown on Read to Write: CAS Latencies (Burst Length = 4 or 8) on page 28. The example is shown for tDQSS(min). The tDQSS(max) case, not shown here, has a longer bus idle time. tDQSS(min) and tDQSS(max) are defined in the section on Writes. A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto Precharge was not activated). The Precharge command should be issued x cycles after the Read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on Read to Precharge: CAS Latencies (Burst Length = 4 or 8) on page 29 for Read latencies of 2 and 2.5. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
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Terminating a Read Burst: CAS Latencies (Burst Length = 8)
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2 DQS DQ
DOa-n
No further output data after this point. DQS tristated. CAS Latency = 2.5
CK CK Command Address
Read
BAa, COL n
NOP
BST
NOP
NOP
NOP
CL=2.5 DQS DQ
DOa-n
No further output data after this point. DQS tristated.
DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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Read to Write: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK CK Command Address
Read
BAa, COL n
BST
NOP
Write
BAa, COL b
NOP
NOP
CL=2 DQS DQ DM
DOa-n
tDQSS (min)
DI a-b
CAS Latency = 2.5
CK CK Command Address
Read BST NOP NOP Write NOP
BAa, COL n
BAa, COL b
CL=2.5 DQS DQ DM
DOa-n
tDQSS (min)
Dla-b
DO a-n = data out from bank a, column n . a-b = data in to bank a, column b DI 1 subsequent elements of data out appear in the programmed order following DO a-n. Data In elements are applied following Dl a-b in the programmed order, according to burst length. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
CAS Latency = 2
CK CK Command
Read NOP PRE NOP NOP ACT
tRP Address
BA a, COL n BA a or all BA a, ROW
CL=2 DQS DQ
DOa-n
CAS Latency = 2.5
CK CK Command
Read NOP PRE NOP NOP ACT
tRP Address
BA a, COL n BA a or all BA a, ROW
CL=2.5 DQS DQ
DOa-n
DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following DO a-n. Shown with nominal tAC, tDQSCK, and tDQSQ.
Don't Care
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Writes Write bursts are initiated with a Write command, as shown on Write Command on page 31. The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic Write commands used in the following illustrations, Auto Precharge is disabled. During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as the write postamble. The time between the Write command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and tDQSS(max)). Write Burst (Burst Length = 4) on page 32 shows the two extremes of tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS enters High-Z and any additional input data is ignored. Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previous Write command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). Write to Write (Burst Length = 4) on page 33 shows concatenated bursts of 4. An example of non-consecutive Writes is shown on Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 34. Full-speed random write accesses within a page or pages can be performed as shown on Random Write Cycles (Burst Length = 2, 4 or 8) on page 35. Data for any Write burst may be followed by a subsequent Read command. To follow a Write without truncating the write burst, tWTR (Write to Read) should be met as shown on Write to Read: NonInterrupting (CAS Latency = 2; Burst Length = 4) on page 36. Data for any Write burst may be truncated by a subsequent Read command, as shown in the figures on Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8) on page 37 to Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8) on page 39. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously. Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write burst, tWR should be met as shown on Write to Precharge: Non-Interrupting (Burst Length = 4) on page 40. Data for any Write burst may be truncated by a subsequent Precharge command, as shown in the figures on Write to Precharge: Interrupting (Burst Length = 4 or 8) on page 41 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8) on page 43. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can be used to truncate bursts.
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Write Command
CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 DIS AP BA0, BA1 BA CA = column address BA = bank address EN AP = enable Auto Precharge DIS AP = disable Auto Precharge Don't Care HIGH
CA EN AP
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Write Burst (Burst Length = 4)
Maximum DQSS
T1 CK CK Command Address
Write
BA a, COL b
T2
T3
T4
NOP
NOP
NOP
tDQSS (max) DQS DQ DM
Dla-b
Minimum DQSS
T1 CK CK Command Address
Write BA a, COL b NOP NOP NOP
T2
T3
T4
tDQSS (min) DQS DQ DM
Dla-b
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. A10 is Low with the Write command (Auto Precharge is disabled).
Don't Care
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Write to Write (Burst Length = 4)
Maximum DQSS
T1 CK CK Command Address
Write NOP Write NOP NOP NOP
T2
T3
T4
T5
T6
BAa, COL b
BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b DI a-n
Minimum DQSS
T1 CK CK Command Address
Write
BA, COL b
T2
T3
T4
T5
T6
NOP
Write
BA, COL n
NOP
NOP
NOP
tDQSS (min) DQS DQ DM
DI a-b DI a-n
DI a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.
Don't Care
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Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)
T1 CK CK Command Address
Write
T2
T3
T4
T5
NOP
NOP
Write
NOP
BAa, COL b
BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b DI a-n
DI a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 subsequent elements of data in are applied in the programmed order following DI a-n. A non-interrupted burst is shown. Each Write command may be to any bank.
Don't Care
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Random Write Cycles (Burst Length = 2, 4 or 8)
Maximum DQSS
T1 CK CK Command Address
Write
BAa, COL b
T2
T3
T4
T5
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
tDQSS (max) DQS DQ DM
DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a'
Minimum DQSS
T1 CK CK Command Address
Write
BAa, COL b
T2
T3
T4
T5
Write
BAa, COL x
Write
BAa, COL n
Write
BAa, COL a
Write
BAa, COL g
tDQSS (min) DQS DQ DM
DI a-b DI a-b' DI a-x DI a-x' DI a-n DI a-n' DI a-a DI a-a' DI a-g
DI a-b, etc. = data in for bank a, column b, etc. b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted). Each Write command may be to any bank.
Don't Care
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2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (max) DQS DQ DM
DI a-b
CL = 2
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWTR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands may be to any bank.
Don't Care
Page 36 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (max) DQS DQ DM
DIa- b
CL = 2
1
1
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP Read NOP
T2
T3
T4
T5
T6
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Page 37 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS Latency = 2; Burst Length = 8)
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
NOP
tWTR Address
BAa, COL b BAa, COL n
tDQSS (min) DQS DQ DM
DI a-b
CL = 2
1
2
2
DI a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element) The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = This bit is correctly written into the memory array if DM is low. Don't Care 2 = These bits are incorrectly written into the memory array if DM is low.
Page 38 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Read: Nominal DQSS, Interrupting (CAS Latency = 2; Burst Length = 8)
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
NOP
tWTR Address
BAa, COL b BAa, COL n
tDQSS (nom) DQS DQ DM
DI a-b
CL = 2
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following DI a-b. tWTR is referenced from the first positive CK edge after the last desired data in pair. The Read command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). The Read and Write commands are not necessarily to the same bank. 1 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Page 39 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Non-Interrupting (Burst Length = 4)
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP NOP PRE
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (max) DQS DQ DM
DI a-b
tRP
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP NOP PRE
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
tRP
DI a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following DI a-b. A non-interrupted burst is shown. tWR is referenced from the first positive CK edge after the last data in pair. A10 is Low with the Write command (Auto Precharge is disabled).
Don't Care
Page 40 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Interrupting (Burst Length = 4 or 8)
Maximum DQSS
T1 CK CK Command
Write NOP NOP NOP PRE NOP
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (max) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
Minimum DQSS
T1 CK CK Command
Write NOP NOP NOP PRE NOP
T2
T3
T4
T5
T6
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst, for burst length = 8. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Page 41 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting (Burst Length = 4 or 8)
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
NOP
tWR Address
BA a, COL b BA (a or all)
tDQSS (min) DQS DQ DM
DI a-b
2
tRP
3
4
4
1
1
DI a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = This bit is correctly written into the memory array if DM is low. 4 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Page 42 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)
T1 CK CK Command
Write
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
NOP
tWR Address
BA a, COL b BA (a or all)
tDQSS (nom) DQS DQ DM
DI a-b
2
tRP
3
3
1
1
DI a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following DI a-b. tWR is referenced from the first positive CK edge after the last desired data in pair. The Precharge command masks the last 2 data elements in the burst. A10 is Low with the Write command (Auto Precharge is disabled). 1 = Can be don't care for programmed burst length of 4. 2 = For programmed burst length of 4, DQS becomes don't care at this point. 3 = These bits are incorrectly written into the memory array if DM is low.
Don't Care
Page 43 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Precharge Command
CK CK CKE CS RAS CAS WE A0-A9, A11, A12 All Banks A10 BA0, BA1 One Bank BA BA = bank address (if A10 is Low, otherwise Don't Care). Don't Care HIGH
Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) is available for a subsequent row access some specified time (tRP) after the Precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any Read or Write commands being issued to that bank.
Page 44 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior to entering Powerdown. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the DDR SDRAM, and all other input signals are "Don't Care". However, powerdown duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down mode. The power-down state is synchronously exited when CKE is registered HIGH (along with a Nop or Deselect command). A valid, executable command may be applied one clock cycle later.
Power Down
CK CK CKE tIS tIS
Command
VALID No column access in progress
NOP
NOP Exit power down mode
VALID
Enter Power Down mode (Burst Read or Write operation must not be in progress)
Don't Care
Page 45 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 2: Clock Enable (CKE)
1. 2. 3. 4. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved.
CKE n-1 Current State Previous Cycle L L L L H H H H CKEn Current Cycle L H L H L L L H Command n Action n Notes
Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active
X Deselect or NOP X Deselect or NOP Deselect or NOP AUTO REFRESH Deselect or NOP See "Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)" on page 47
Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry 1
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Page 46 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State Any CS H L L Idle L L L Row Active L L Read (Auto Precharge Disabled) L L L L L L RAS X H L L L H H L H L H H H L CAS X H H L L L L H L H H L L H WE X H H H L H L L H L L H L L Command Deselect No Operation Active AUTO REFRESH MODE REGISTER SET Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column and start Read burst Select column and start Write burst Truncate Write burst, start Precharge Action NOP. Continue previous operation NOP. Continue previous operation Select and activate row Notes 1-6 1-6 1-6 1-7 1-7 1-6, 10 1-6, 10 1-6, 8 1-6, 10 1-6, 8 1-6, 9 1-6, 10, 11 1-6, 10 1-6, 8, 11
Write (Auto Precharge Disabled)
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according Truth Table 4. 5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 11. Requires appropriate DM masking. 2003-01-09, V1.1
Page 47 of 77
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
Current State Any Idle CS H L X L Row Activating, Active, or Precharging L L L Read (Auto Precharge Disabled) L L L L Write (Auto Precharge Disabled) L L L L Read (With Auto Precharge) L L L L Write (With Auto Precharge) L L L RAS X H X L H H L L H L L H H L L H H L L H H L CAS X H X H L L H H L H H L L H H L L H H L L H WE X H X H H L L H H L H H L L H H L L H H L L Command Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Select and activate row Select column and start Read burst Select column and start new Write burst Select and activate row Select column and start new Read burst Select column and start Write burst Select and activate row Select column and start Read burst Select column and start new Write burst Select and activate row Select column and start new Read burst Select and activate row Select column and start Read burst Select column and start Write burst Action NOP/continue previous operation NOP/continue previous operation Notes 1-6 1-6 1-6 1-6 1-7 1-7 1-6 1-6 1-7 1-6 1-6 1-8 1-7 1-6 1-6 1-7,10 1-7,9,10 1-6 1-6 1-7,10 1-7,10 1-6
1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See note 10. Write with Auto Precharge Enabled: See note 10. 4. AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8. Requires appropriate DM masking. 9. A Write command may be applied after the completion of data output. 10. Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in table 5.
Page 48 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank) Read or Read w/AP
Minimum Delay with Concurrent Auto Precharge Support 1 + (BL/2) + tWTR BL/2 1 BL/2 CL (rounded up)+ BL/2 1
Units
tCK tCK tCK tCK tCK tCK
WRITE w/AP
Write ot Write w/AP Precharge or Activate Read or Read w/AP
Read w/AP
Write or Write w/AP Precharge or Activate
Page 49 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Simplified State Diagram
Power Applied Power On
Precharge PREALL
Self Refresh REFS REFSX
MRS EMRS
MRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
ACT
Precharge Power Down
Write Write A Write
Row Active
Burst Stop Read
Read A Read Read
Write A Read A Write A PRE PRE PRE
Read A
Read A
PRE
Precharge PREALL Automatic Sequence Command Sequence
PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh REFA = Auto Refresh
CKEL = Enter Power Down CKEH = Exit Power Down ACT = Active Write A = Write with Autoprecharge Read A = Read with Autoprecharge PRE = Precharge
Page 50 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Operating Conditions Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to VSS Voltage on Inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Units V V V V
-0.5 to VDDQ+ 0.5 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6
0 to +70
C C
W mA
-55 to +150
1.0 50
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Input and Output Capacitances
Parameter Input Capacitance: CK, CK BGA TSOP Delta Input Capacitance CK, CK BGA TSOP Input Capacitance: All other input-only pins BGA TSOP Delta Input Capacitance: All other input-only pins BGA TSOP Input/Output Capacitance: DQ, DQS, DM BGA TSOP Delta Input/Output Capacitance : DQ, DQS, DM BGA CdIO CIO CdI2 CI2 CdI1 Package TSOP CI1 Symbol Min. 2.0 1.5 2.0 1.5 4.0 3.5 Max. 3.0 pF 2.5 0.25 pF 0.25 3.0 pF 2.5 0.5 pF 0.5 5.0 pF 4.5 0.5 pF 0.5 1 1, 2 1 1 1 1 Units Notes
1. These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5V 0.2V, f = 100MHz, TA = 25C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) 0.2V. Unused pins are tied to ground . 2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level
Page 51 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics and DC Operating Conditions
(0C TA 70C; VDDQ = 2.5V 0.2V, VDD = + 2.5V 0.2V )
Symbol VDD VDDQ Supply Voltage I/O Supply Voltage Parameter Min 2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 2 5 Units V V V V V V V V V 1, 2 1, 3 1 1 1 1, 4 5 Notes 1 1
VSS, VSSQ Supply Voltage, I/O Supply Voltage VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIRatio II IOZ IOH IOL I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pullup Current to Pulldown Current Input Leakage Current. Any input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current, Normal Strength Driver (VOUT = 1.95 V, VTT = 1.13 V) Output Low Current, Normal Strength Driver (VOUT = 0.35 V, VTT = 1.17 V)
- 0.3 - 0.3
0.36 0.71
-2 -5 - 16.2
16.2
mA mA
mA mA
1 1 1 1
1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 4. VID is the magnitude of the difference between the input level on CK and the input level on CK 5. The ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Page 52 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Normal Strength Pulldown and Pullup Characteristics
1. The nominal pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 2. The full variation in driver pulldown current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve.
Normal Strength Pulldown Characteristics
140 120 1OUT (mA) 100 80 60 40 20 0 0 0.5 1 VOUT (V) 3. The nominal pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 4. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve. 1.5 2 2.5 Nominal Low Minimum Maximum
Nominal High
Normal Strength Pullup Characteristics
0 -20 -40 1OUT (mA) -60 -80 -100 -120 -140 -160 Maximum 0 0.5 1 1.5 VOUT (V) 2 2.5 Nominal High Nominal Low Minimum
5. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. The full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0V.
Page 53 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Normal Strength Pulldown and Pullup Currents
Pulldown Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Nominal Low 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Nominal High 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Min 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Max 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Nominal Low Pullup Current (mA) Nominal High Min Max
-6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5
-52.7 -52.8
-7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5
-155.3 -160.1
-4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -33.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0
-41.1 -41.2
-10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6
-192.9 -198.2
Evaluation Conditions for I/O Driver Characteristics
Nominal Operating Temperature VDD / VDDQ Process Corner 25 C 2.5V typical Minimum 70 C 2.3V slow-slow Maximum 0 C 2.7V fast-fast
Page 54 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Weak Strength Pulldown and Pullup Characteristics Weak Strength Pulldown Characteristics
80 70 60
Maximum Typical high Typical low Minimum
Iout [mA]
50 40 30 20 10 0 0,0 0,5 1,0 1,5 2,0
2,5
Vout [V]
1. The weak pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve 2. The weak pullup V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 3. The full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the V-I curve.
Weak Strength Pullup Characteristics
0,0 0,0 -10,0 -20,0 -30,0
Minimum
0,5
1,0
1,5
2,0
2,5
Iout [V]
Typical low
-40,0 -50,0 -60,0 -70,0 -80,0
Typical high
Maximum
Vout [V]
4. The full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. The full variation in the ratio of the nominal pullup to pulldown current should be unity 10%, for device drain to source voltages from 0.1 to 1.0V.
2003-01-09, V1.1
Page 55 of 77
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Weak Strength Driver Pulldown and Pullup Currents
Pulldown Current (mA) Voltage (V) Nominal Low Nominal High Min Max Nominal Low Pullup Current (mA) Nominal High Min Max
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7
3.4 6.9 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8
3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6
2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6
5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7
-3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9
-4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8
-2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3
-5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
Evaluation Conditions for I/O Driver Characteristics
Nominal Operating Temperature VDD / VDDQ Process Corner 25 C 2.5V typical Minimum 70 C 2.3V slow-slow Maximum 0 C 2.7V fast-fast
Page 56 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
IDD Specification and Conditions
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V)
Symbol Parameter/Condition DDR200 -8 typ. Operating Current: one bank; active / precharge; tRC = tRC MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles Operating Current: one bank; active/read/precharge; burst length 4; Refer to the following page for detailed test conditions. x4/x8 x16 x4/x8 x16 70 72 80 83 max. 90 95 100 105 DDR266A -7 typ. 75 77 90 94 max. 100 105 110 115 DDR266 -7F typ. 83 86 98 102 max. 110 115 120 125 DDR333 -6 typ. 85 88 100 104 max. 110 115 120 125 mA 1, 2 mA mA 1, 2 mA Notes Unit 4
IDD0
IDD1
IDD2P
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX
5
7
6
8
6
8
6
9
mA
1, 2
Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; IDD2F CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; IDD2Q CKE >= VIH MIN; address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM. x4/x8 x16 x4/x8 x16 x4/x8 x16
30
35
35
40
35
40
45
55
mA
1, 2
18
22
20
25
20
25
25
28
mA
1, 2
IDD3P
13
16
15
18
15
18
18
21
mA
1, 2
Active Standby Current: one bank active; CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank active; BL2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of IDD4R data outputs changing on every clock edge; CL2 for DDR200 and DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; IDD4W 50% of data outputs changing on every clock edge; CL2 for DDR200 and DDR266(A), CL3 for DDR333 and DDR400 IDD3N IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh
40 42 79 89 85 96
45 50 95 110 105 120
50 52 95 107 105 119
55 60 115 130 125 140
50 52 95 107 105 119
55 60 115 130 125 140
60 63 110 124 125 141
65 70 140 160 145 165
mA 1, 2 mA mA 1, 2 mA mA 1, 2 mA
126
170
135
180
135
180
144
190
mA
1, 2
standard version IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on low power version Operating Current: four bank; four bank interleaving with burst length 4; Refer to the following page for detailed test conditions. x4/x8 x16
1.5 1.20 150 158
2.5 1.25 210 220
1.5 1.20 171 180
2.5 1.25 225 235
1.5 1.20 171 180
2.5 1.25 225 235
1.5 1.20 208 218
2.5 1.25 270
mA 1, 2, 3 mA
IDD7
mA 285
1, 2
1. IDD specifications are tested after the device is properly initialized and measured at 100 MHz for DDR200, 133 MHz for DDR266(A) and 166 MHz for DDR333 2. Input slew rate = 1V/ns. 3. Enables on-chip refresh and address counters 4. Test condition for typical values : VDD = 2.5V ,Ta = 25C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10C
Page 57 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Detailed test conditions for DDR SDRAM IDD1 and IDD7
IDD1 : Operating current : One bank operation
1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0 mA 2. Timing patterns - DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRCD = 2 * tCK, tRAS = 5 * tCK Setup: A0 N R0 N N P0 N Read : A0 N R0 N N P0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing 50% of data changing at every burst - DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRCD = 3 * tCK, tRC = 9 * tCK, tRAS = 5 * tCK Setup: A0 N N R0 N P0 N N N Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing 50% of data changing at every burst 3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0 mA 2. Timing patterns - DDR200 (100Mhz, CL=2) : tCK = 10 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD= 3 * tCK, Read with autoprecharge Setup: A0 N A1 R0 A2 R1 A3 R2 Read : A0 R3 A1 R0 A2 R1 A3 R2- repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2) : tCK = 7.5 ns, CL=2, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst - DDR333 (166Mhz, CL=2.5) : tCK = 6 ns, CL=2.5, BL=4, tRRD = 2 * tCK, tRCD = 3 * tCK Setup: A0 N A1 R0 A2 R1 A3 R2 N R3 Read : A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing 50% of data changing at every burst 3.Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Page 58 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
AC Characteristics
(Notes 1-6 apply to the following Tables: Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. The figure below represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level) 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating,DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification for DDR components
AC Output Load Circuit Diagram / Timing Reference Load VTT
50W Output (VOUT) Timing Reference Point
30pF
AC Operating Conditions )
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V)
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 1. 2. 3. 4. Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS, and DM Signals Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs 0.7 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 Max Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
0.5*VDDQ - 0.2 0.5*VDDQ + 0.2
Input slew rate = 1V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Page 59 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing - Absolute Specifications
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V) (Part 1 of 2)
DDR200 -8 Min tAC DQ output access time from CK/CK Max DDR266A -7 Min Max DDR266 -7F Min Max DDR333 -6 Min Max
Symbol
Parameter
Unit
Notes
- 0.8 - 0.8
0.45 0.45
+ 0.8 + 0.8
0.55 0.55
- 0.75 - 0.75
0.45 0.45
+ 0.75 + 0.75
0.55 0.55
- 0.75 - 0.75
0.45 0.45
+ 0.75 + 0.75
0.55 0.55
- 0.7 - 0.6
0.45 0.45
+ 0.7 + 0.6
0.55 0.55
ns ns tCK tCK ns ns ns ns ns ns ns ns
1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4,10 1-4, 10 1-4, 5 1-4, 5 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 7 1-4, 6 1-4
tDQSCK DQS output access time from CK/CK tCH tCL tHP tCK tCK tCK tDH tDS tIPW tDIPW tHZ tLZ tDQSS DQ and DM input hold time DQ and DM input setup time Control & Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS & associated DQ signals) Data hold skew factor TSOP66 BGA TSOP66 BGA DQ output hold time from DQS DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Clock cycle time CK high-level width CK low-level width Clock Half Period CL = 3.0 CL = 2.5 CL = 2.0
min (tCL, tCH) 8 8 10 0.6 0.6 2.5 2.0 12 12 12
min (tCL, tCH) 7 7 7.5 0.5 0.5 2.2 1.75 12 12 12
min (tCL, tCH) 7 7 7.5 0.5 0.5 2.2 1.75 12 12 12
min (tCL, tCH) 6 6 7.5 0.45 0.45 2.2 1.75 12 12 12
- 0.8 - 0.8
0.75
+ 0.8 + 0.8
1.25
- 0.75 - 0.75
0.75
+ 0.75 + 0.75
1.25
- 0.75 - 0.75
0.75
+ 0.75 + 0.75
1.25
- 0.7 - 0.7
0.75
+ 0.7 + 0.7
1.25
ns ns tCK ns ns ns ns
ns
+ 0.6 + 0.6
1.0 1.0 tHP-tQHS 0.35 0.2 0.2 2 0 0.40 0.25 0.60 tHP-tQHS 0.35 0.2 0.2 2 0 0.40 0.25 0.9 1.0 0.9 1.0
+ 0.5 + 0.5
0.75 0.75 tHP-tQHS 0.35 0.2 0.2 2 0 0.60 0.40 0.25 0.9 1.0 0.9 1.0
+ 0.5 + 0.5
0.75 0.75 tHP-tQHS 0.35 0.2 0.2 2 0 0.60 0.40 0.25 0.75 0.8 0.75 0.8
+ 0.45 + 0.40
0.55 0.5
tDQSQ
tQHS tQH tDQSL,H tDSS tDSH tMRD
tCK tCK tCK tCK ns 0.60 tCK tCK ns ns ns ns
tWPRES Write preamble setup time tWPST tWPRE tIS Write postamble Write preamble Address and control input setup time Address and control input hold time fast slew rate slow slew rate fast slew rate slow slew rate
1.1 1.1 1.1 1.1
2-4, 10,11
tIH
Page 60 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing - Absolute Specifications
(0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V) (Part 2 of 2)
DDR200 -8 Min tRPRE tRPST tRAS tRC tRFC tRCD tRP tRAP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval (8192 refresh commands per 64ms refresh period) 1 80 200 7.8 1 75 200 7.8 0.9 0.40 50 70 80 20 20 20 15 15 Max 1.1 0.60 120,000 DDR266A -7 Min 0.9 0.40 45 65 75 20 20 20 15 15 Max 1.1 0.60 120,000 DDR266 -7F Min 0.9 0.40 45 60 75 15 15 20 15 15 (twr/tck) + (trp/tck) 1 75 200 7.8 1 75 200 7.8 Max 1.1 0.60 120,000 DDR333 -6 Min 0.9 0.40 42 60 72 18 18 18 12 15 Max 1.1 0.60 70,000 tCK tCK ns ns ns ns ns ns ns ns tCK tCK ns tCK 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4 1-4,9 1-4 1-4 1-4 1-4, 8
Symbol
Parameter
Unit
Notes
ms
1. Input slew rate >= 1V/ns for DDR266 & DDR333 and = 1V/ns for DDR 200 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarilty tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between VOH(ac) and VOL(ac)
Page 61 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Electrical Characteristics & AC Timing for DDR266 - Applicable Specifications Expressed in Clock Cycles (tCK=133Mhz) (0 C TA 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V,
tCK = 133MHz Symbol tMRD tWPRE tRAS tRC tRFC tRCD Parameter Mode register set command cycle time Write preamble Active to Precharge command DDR266A Active to Active/Auto-refresh command period DDR266 Auto-refresh to Active/Auto-refresh command period DDR266A Active to Read or Write delay DDR266 DDR266A tRP tRRD tWR tDAL tWTR tXSNR tXSRD Precharge command period DDR266 Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command 2 2 2 5 1 10 200 2 3 8 10 3 sort Min 2 0.25 6 9 16000 Max tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK 1-54 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 1-5 Units Notes
1. Input slew rate = 1V/ns 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Page 62 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Timing Diagrams Data Input (Write)
(Timing Burst Length = 4)
tDQSL tDQSH DQS tDH tDS DQ
DI n
tDH tDS DM
DI n = Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n.
Don't Care
Data Output (Read)
(Timing Burst Length = 4)
DQS tDQSQ max tQH
DQ
tQH (Data output hold time from DQS) tDQSQ and tQH are only shown once and are shown referenced to different edges of DQS, only for clarify of illustration. . tDQSQ and tQH both apply to each of the four relevant edges of DQS. tDQSQ max. is used to determine the worst case setup time for controller data capture. tQH is used to determine the worst case hold time for controller data capture.
Page 63 of 77
2003-01-09, V1.1
VDD
* VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latchup. ** tMRD is required before any command can be applied and 200 cycles of CK are required before a Read command can be applied. The two Autorefresh commands may be moved to follow the first MRS, but precede the second Precharge All command.
Page 64 of 77
tVTD tCK tCH
VDDQ
VTT (System*)
VREF
200 cycles of CK**
tCL tMRD tMRD tRP tRFC tRFC tMRD
200ms
CK CK
tIH tIS
Initialize and Mode Register Sets
CKE
tIH tIS NOP PRE EMRS MRS PRE AR AR
LVCMOS LOW LEVEL
Command
MRS
ACT
DM
tIH tIS CODE tIH tIS CODE CODE tIS tIH tIS CODE RA tIH CODE CODE RA
A0-A9, A11, A12
A10
ALL BANKS
tIH tIS BA0=H BA1=L
ALL BANKS
BA0, BA1
BA0=L BA1=L
BA0=L BA1=L
BA
High-Z
DQS
High-Z
DQ
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
2003-01-09, V1.1
Power-up: VDD and CK stable
Don't Care
Extended Mode Register Set
Load Mode Register, Reset DLL
Load Mode Register (with A8 = L)
Page 65 of 77
tCK tCH tCL tIH tIS tIS tIH NOP NOP VALID tIH VALID VALID
Enter Power Down Mode
CK
Power Down Mode
CK
tIS
CKE
tIS
Command
VALID*
tIS
ADDR
DQS
DQ
DM
Exit Power Down Mode
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
No column accesses are allowed to be in progress at the time power down is entered. * = If this command is a Precharge (or if the device is already in the idle state) then the power down mode shown is Precharge power down. If this command is an Active (or if at least one row is already active), then the power down mode shown is Active power down.
2003-01-09, V1.1
Don't Care
Page 66 of 77
tRP tCH tCK tRFC tRFC tCL VALID VALID PRE NOP NOP AR NOP AR NOP NOP ACT RA RA
Auto Refresh Mode
CK CK
tIH
tIS
CKE
tIH
tIS
Command
NOP
A0-A8
A9, A11,A12
ALL BANKS
A10
ONE BANK
tIH tIS BANK(S)
RA
BA0, BA1
BA
DQS
DQ
DM
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. DM, DQ, and DQS signals are all don't care/high-Z for operations shown.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
2003-01-09, V1.1
Don't Care
Page 67 of 77
Clock must be stable before exiting Self Refresh Mode
tRP* tCK tCH tCL
Self Refresh Mode
200 cycles
CK CK
tIH tIS tIS
tIS
CKE
tIH tXSRD, tXSRN NOP AR NOP VALID
tIS
Command
tIH tIS VALID
ADDR
DQS
DQ
DM
Enter Self Refresh Mode
Exit Self Refresh Mode
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
* = Device must be in the all banks idle state before entering Self Refresh Mode. ** = tXSNR is required before any non-read command can be applied, and tXSRD (200 cycles of CK). are required before a Read command can be applied.
Don't Care
2003-01-09, V1.1
tCK tCH tRP
tCL
Page 68 of 77
tIH tIS VALID tIH tIS NOP NOP PRE NOP NOP ACT NOP NOP NOP tIH tIS Read VALID VALID tIH
CK CK
CKE
Command
A0-A9, A11, A12
COL n
RA tIH tIS
ALL BANKS
RA
A10
DIS AP ONE BANK
tIH tIS BA x BA x* BA x
BA0, BA1
DM
tLZ (min) tRPRE
Read without Auto Precharge (Burst Length = 4)
DQS
tAC (min) tRPST tDQSCK (min) tHZ (min)
Case 1: tAC/tDQSCK = min
CL=2 DO n
tLZ (max) tRPRE
DQ
DQS
tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max
DQ
DO n
DO n = data out from column n.
3 subsequent elements of data out are provided in the programmed order following DO n.
Don't Care
DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
2003-01-09, V1.1
NOP commands are shown for ease of illustration; other commands may be valid at these times.
tCK tCH tRP
tCL
CK
Page 69 of 77
tIH tIS VALID tIH tIS VALID VALID tIH
CK
CKE
Command
tIH tIS COL n tIH tIS RA RA
NOP
Read NOP NOP NOP NOP ACT NOP NOP NOP
A0-A9, A11, A12
A10
EN AP
tIH tIS BA x BA x
BA0, BA1
Read with Auto Precharge (Burst Length = 4)
DM
tLZ (min) tRPRE
DQS
tLZ (min) tAC (min) tRPST tDQSCK (min) tHZ (min)
Case 1: tAC/tDQSCK = min
CL=2 DO n
tLZ (max) tRPRE
DQ
DQS
tAC (max) tLZ (max) tHZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max
DQ
DO n
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
2003-01-09, V1.1
DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. EN AP = enable Auto Precharge. ACT = active; RA = row address. NOP commands are shown for ease of illustration; other commands may be valid at these times.
Don't Care
tCK tCH
tCL
CK CK
tIH tIS VALID tIH tIS NOP NOP Read NOP PRE NOP NOP ACT NOP tIH tIS RA COL n tIH tIS ALL BANKS RA ONE BANK RA ACT tRC
Page 70 of 77
RA DIS AP
tIH tIS BA x BA x BA x* BA x tLZ (min) tRPRE tRP tRCD tRAS tLZ (min) tHZ (min) tAC (min) tRPST tDQSCK (min)
CKE
Command
A0-A9, A11, A12
Bank Read Access (Burst Length = 4)
A10
BA0, BA1
DM
DQS
Case 1: tAC/tDQSCK = min
CL=2
DQ
DO n
tLZ (max) tRPRE
DQS
tHZ (max) tAC (max) tLZ (max) tRPST tDQSCK (max)
Case 2: tAC/tDQSCK = max
DQ
DO n
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
DO n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following DO n. DIS AP = disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2003-01-09, V1.1
Don't Care
tCH tCK tCL tRP tWR
CK
Page 71 of 77
tIH VALID Write NOP NOP NOP NOP PRE NOP NOP ACT tIH tIS COL n RA tIH tIS
CK
tIH
tIS
CKE
tIH
tIS
Command
NOP
A0-A9, A11, A12
ALL BANKS
RA
A10 ONE BANK
tIH tIS BA x tWPRE tWPRES tDQSH tDQSS tWPST tDQSL tDSH BA x*
DIS AP
Write without Auto Precharge (Burst Length = 4)
BA0, BA1
BA
DQS
DIn
DQ
DM
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
tDQSS = min. DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
2003-01-09, V1.1
Don't Care
tCH tCK tCL tRP tWR
CK
Page 72 of 77
tDAL VALID VALID VALID Write NOP NOP NOP NOP NOP NOP NOP ACT tIH tIS COL n tIH tIS RA
CK
tIH
tIS
CKE
tIH
tIS
Command
NOP
A0-A9, A11, A12
A10
tIH tIS BA x
Write with Auto Precharge (Burst Length = 4)
EN AP
RA
BA0, BA1
tDSH tDQSH tDQSL tWPST
BA
tWPRES tDQSS
DQS
DIn
DQ
DM
tWPRE
tDQSS = min.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
2003-01-09, V1.1
DIn = Data in for column n. 3 subsequent elements of data in are applied in the programmed order following DIn. EN AP = Enable Auto Precharge. ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
Don't Care
tCH tCK tCL
CK
Page 73 of 77
tIH VALID tIH tRAS NOP ACT NOP Write NOP NOP NOP NOP PRE NOP tIH tIS RA Col n tIH tIS RA
CK
tIS
CKE
tIS
Command
Bank Write Access (Burst Length = 4)
A0-A9, A11, A12
ALL BANKS ONE BANK
A10
tIH tIS BA x tRCD tWPRES tDQSH tDQSS tDQSL tWPST tDSH BA x
DIS AP
BA0, BA1
BA x
tWR
DQS
DIn
DQ
DM
tWPRE
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
tDQSS = min. DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n. DIS AP = Disable Auto Precharge. * = don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
2003-01-09, V1.1
Don't Care
tCH tCK tCL
CK
Page 74 of 77
VALID Write NOP NOP NOP NOP PRE NOP NOP ACT tIH tIS COL n RA tIH tIS
CK
tIH
tIS
CKE
tIH
tIS
Command
NOP
A0-A9, A11, A12
Write DM Operation (Burst Length = 4)
ALL BANKS
RA
A10 ONE BANK
tIH tIS BA x tDSS tWPRES tDQSH tDQSS tDQSL tWPST tDSH tWR BA x*
DIS AP
BA0, BA1
BA
tRP
DQS
DIn
DQ
DM
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
DI n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked). DIS AP = Disable Auto Precharge. * = Don't care if A10 is High at this point. PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. tDQSS = min.
2003-01-09, V1.1
Don't Care
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B
Package Dimensions
60 balls FBGA-Package
12mm x 8mm
Plastic Package, P-TSOPII-66 (400mil; 66 lead) Thin Small Outline Package
0,05 min
1,20 max
0,25 Basic
G a u g e P la n e 1 0 ,1 6 0 ,1 3
0 ,6 5 B a s ic 0 ,3
0,0 8
0 ,5 0 ,1 1 1 ,7 6 0 ,2
0 ,8 0 5 R E F
0 .1 S e a tin g P la n e
Lead #1
2 2 ,2 2 0 ,1 3
TSOP66
Page 75 of 77
2003-01-09, V1.1
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1 TABLE OF CONTENT
Features Description Pin Configuration TSOP Pin Configuration BGA Input/Output Functional Description Ordering Information Block Diagram (32Mb x 4) Block Diagram (16Mb x 8) Block Diagram (8Mb x 16) Functional Description Initialization Register Definition Mode Register Operation Burst Definition Required CAS Latencies Extended Mode Register Extended Mode Register Definition Commands Delesect, No Operation Mode Register Set Active Read Write Precharge Auto Precharge Burst Terminate Auto Refresh Self Refresh Truth Table 1a: Commands Truth Table 1b: DM Operation 1 1 2 3 4 5 6 7 8 9 10 10 11 12 13 14 15 16 16 16 16 16 16 16 17 17 17 17 18 18 Write to Write Random Write Cycles Write to Read Write to Read Interrupting Write to Read: Minimum DQSS Write to Read: Nominal DQSS Write to Precharge Non-Interrupting Write to Precharge Interrupting Write to Precharge Minimum DQSS Write to Precharge: Nominal DQSS Precharge Power-Down Truth Table 2: Clock Enable (CKE) Truth Table 3: Current State, SameBank) Truth Table 4: Current State,Different Bank Truth Table 5: Concurrent Auto Precharge Simplified State Diagram Operating Conditions Absolute Maximum Ratings Input and Output Capacitances DC Electrical Operating Conditions Normal Strength Characterisitcs Weak Strength Characterisitcs IDD Specifications and Conditions AC Characteristics AC Output Load Circuit Diagram Electrical Characteristics & AC Timing Timing Diagrams Data Input (Write) Data Output (Read) Initialize and Mode Register Sets Power Down Mode Auto Refresh Mode Self Refresh Mode Read without Auto Precharge Read with Auto Precharge Bank Read Access Write without Auto Precharge. Write with Auto Precharge Bank Write Access Write DM Operation Package Dimensions Table of Content Security Information 34 35 36 37 38 40 40 41 42 43 44 45 46 47 48 49 50 51 51 51 52 53 55 57 59 59 60 63 63 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77
Operations Activating a Specific Row in a Specific Bank tRCD and tRRD Definition Read Command Read Burst Consecutive Read Bursts Non-Consecutive Read Bursts Random Read Accesses Terminating a Read Burst Read to Write Read to Precharge Write Command Write Burst (Burst Length = 4) Write to Write (Burst Length = 4)
2003-01-09, V1.1
19 19 20 21 22 23 24 25 26 27 29 30 32 33
Page 76 of 77
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1 Attention please !
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. This information describes the type of components and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact INFINEON Technologies Offices in Munich or the INFINEON Technologies Sales Offices and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest INFINEON Technologies office or representative. Packing Please use the recycling operators known to you. We can help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of INFINEON Technologies, may only be used in lifesupport devices or systems2 with the express written approval of INFINEON Technologies. 1. A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect the safety or effectiveness of that device or system. 2. Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
2003-01-09, V1.1
Page 77 of 77

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